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| HM674100H Series 1,048,576-word x 4-bit High Speed Static Random Access Memory Features * * * * * * * 1,048,576-word x 4-bit organization. Directly TTL compatible input and output. +5 V Single supply. Completely static memory. No clock or timing strobe required. Super fast access time: 15/20/25 ns (max). Revolutional pin arrangement. Ordering Information Type No. HM674100HJP-15 HM674100HJP-20 HM674100HJP-25 Access Time Package 15 ns 20 ns 25 ns 400 mil 32 pin plastic SOJ (CP-32DB) HM674100H Series Pin Arrangement A0 A1 A2 A3 A4 CS I/O1 VCC VSS I/O2 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top View) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A19 A18 A17 A16 A15 OE I/O4 VSSO VCCO I/O3 A14 A13 A12 A11 A10 NC Pin Description Pin Name A0 to A19 I/O1 to I/O4 WE CS OE VCC VCCO VSSO VSS NC Function Address input input/output Write enable Chip select Output enable +5 V Power supply Output buffer power supply Output buffer ground Ground Not connect 2 HM674100H Series Block Diagram A5 A18 A1 A6 A13 A7 A12 A8 A4 A16 I/O1 I/O2 I/O3 I/O4 V CC V SS Row Decoder Memory Matrix 1024 x 4096 Column I/O Input Data Control Column Decoder A14 A2 A17 A3 A19 A0 A11 A9 A10A15 CS WE OE V CCO V SSO Function Table Input CS H L L L L WE X H H L L OE X H L H L Mode Not selected I/O Pin High-Z VCC Current I SB , I SB1 I CC, I CC1 I CC, I CC1 I CC, I CC1 I CC, I CC1 Ref. Cycle -- -- Read Cycle (1), (2), (3) Write Cycle (1), (2), (3), (4) Write Cycle (5), (6) Output disabled High-Z Read Write Write Data Out Data In Data In Note: X: H or L 3 HM674100H Series Absolute Maximum Ratings Parameter Supply voltage *1 *1 Symbol VCC VT PT Topr Tstg (Bias) Tstg Value -0.5 to +7.0 -0.5 to VCC + 0.5 1.0/1.5 *2 Unit V V W C C C Voltage on any pin relative to V SS Power dissipation Operating temperature range 0 to +70 -10 to +85 -55 to +125 Storage temperature range (with bias) Storage temperature range Notes: 1 With respect to V SS = VSSO 2 PT = 1.5 W is guaranteed under the minimum air flow exceeding 500 linear feet per minute. Under the DC and AC specifications shown in the Tables, this device is tested under the minimum transverse air flow exceeding 500 linear feet per minute. Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Supply voltage Symbol VCC, VCCO VSS , VSSO Input high voltage Input low voltage VIH VIL Min 4.5 0.0 2.2 -0.5 Typ 5.0 0.0 -- -- Max 5.5 0.0 VCC + 0.5 0.8 Unit V V V V 4 HM674100H Series DC Characteristics (VCC = VCCO = 5.0 V 10%, VSS = VSSO = 0 V, Ta = 0 to +70C) HM674100H -15 Parameter Input leakage current Output leakage current -20 -25 A A Symbol Min Max Min Max Min Max Unit Test Conditions |ILI| |ILO | -- -- 2 10 -- -- 2 10 -- -- 2 10 VCC = 5.5 V, VIN = 0 V to VCC CS = VIH or OE = VIH, WE = VIL VI/O = 0 V to VCC CS = VIL, II/O = 0 mA min cycle, II/O = 0 mA CS = VIH, VIN = VIH or VIL CS V CC - 0.2 V VIN 0.2 V or V IN VCC - 0.2 V I OL = 8 mA I OH = -4 mA Operating power supply current I CC Average operating current Standby power supply current I CC1 I SB I SB1 -- -- -- -- 120 -- 220 -- 100 -- 10 -- 120 200 80 10 -- -- -- -- 120 mA 160 mA 60 10 mA mA Output low voltage Output high voltage VOL VOH -- 2.4 0.4 -- -- 2.4 0.4 -- -- 2.4 0.4 -- V V Capacitance (Ta = 25C, f = 1 MHz) Parameter Input capacitance Input/Output capacitance Note: Symbol CIN CI/O *1 *1 Max 6 10 Unit pF pF Test Conditions VIN = 0 V VI/O = 0 V 1. This parameter is sampled and not 100% tested. 5 HM674100H Series AC Characteristics (VCC = VCCO = 5 V 10%, V SS = VSSO = 0 V, Ta = 0 to +70C, unless otherwise noted.) Test Conditions * * * * * Input pulse levels: VSS to 3.0 V Input timing reference levels: 1.5V Input rise and fall time: 4 ns Output reference levels: 1.5 V Output Load: See figure +5V +5V Output 255 480 30 pF *1 Output 255 480 5 pF *1 Output Load A Output Load B (for tHZ, tLZ, tOHZ, tOLZ, tWZ, & tOW) Note: including scope and jig capacitance 6 HM674100H Series Read Cycle HM674100H -15 Parameter Read cycle time Address access time Chip select access time Chip selection to output in low-Z Output enable to output Valid Output enable to output in low-Z Chip deselection to output in high-Z Output hold from address change Symbol t RC t AA t ACS t LZ *1,*2 -20 Max -- 15 15 -- 8 -- 7 -- Min 20 -- -- 5 -- 2 0 5 Max -- 20 20 -- 10 -- 8 -- -25 Min 25 -- -- 5 -- 2 0 5 Max -- 25 25 -- 15 -- 15 -- Unit ns ns ns ns ns ns ns ns Min 15 -- -- 5 -- t OE t OLZ t HZ *1,*2 *1,*2 2 0 5 t OH Notes: 1. This parameter is sampled and not 100% tested. 2. Transition is measured 200 mV from steady state voltage with specified loading in Load (B). 7 HM674100H Series Timing Waveforms Read Cycle-1 t RC Address t AA OE t OE CS t OLZ t OHZ t HZ Valid data High Impedance Note: 1. WE = VIH t OH t ACS t LZ Data Out Read Cycle-2 t RC Address t OH Data Out Previous valid data t AA Valid data t OH Note: 1. WE = VIH 2. CS = VIL 3. OE = VIL 8 HM674100H Series Read Cycle-3 t RC CS t ACS t LZ Data Out High Impedance Note: 1. WE = VIH 2. OE = VIL 3. Address valid prior to or coincident with CS transition low. Valid data t HZ Write Cycle HM674100H -15 Parameter Write cycle time Chip selection to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time Write enable to output in high Z Symbol t WC t CW t AW t AS t WP t WR t DW t DH t WZ *2, *3 *2, *3 *2, *3 *1 -20 Max -- -- -- -- -- -- -- -- 7 7 -- Min 20 15 15 0 15 3 10 0 0 0 2 Max -- -- -- -- -- -- -- -- 8 8 -- -25 Min 25 17 17 0 17 3 15 0 0 0 2 Max -- -- -- -- -- -- -- -- 12 10 -- Unit ns ns ns ns ns ns ns ns ns ns ns Min 15 12 12 0 12 3 8 0 0 0 2 Output disable to output in high Z t OHZ Output active from end of write t OW Notes: 1. All write cycle timings are referred from the last valid address to the first transitioning address. 2. This parameter is sampled and not 100% tested. 3. Transition is measured 200 mV from steady state voltage with specified loading in Load (B). 9 HM674100H Series Write Cycle-1 (OE = H, WE Controlled) t WC Address t CW CS t AS WE t AW t WP *1 t WR t DW Data In Valid data t DH Data Out High Impedance Note: 1. A write occurs during the overlap of a low CS and a low WE (tWP). 10 HM674100H Series Write Cycle-2 (OE = H, CS Controlled) t WC Address t AS CS t AW WE t WP *1 t CW t WR t DW Data In Valid data t DH Data Out High Impedance Note: 1. A write occurs during the overlap of a low CS and a low WE (tWP). 11 HM674100H Series Write Cycle-3 (OE = Clocked, WE Controlled) t WC Address OE t CW CS t AS WE t OHZ Data Out *2 t AW t WP *1 t WR t OLZ High Impedance t DH *2 t DW Data In High Impedance Valid data High Impedance Notes: 1. A write occurs during the overlap of a low CS and a low WE (tWP). 2. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 12 HM674100H Series Write Cycle-4 (OE = Clocked, CS Controlled) t WC Address OE t AS CS *2 t CW t AW t WP WE t DW Data In High Impedance Valid data *1 t WR t DH Data Out Notes: 1. A write occurs during the overlap of a low CS and a low WE (tWP). 2. If CS low transition occurs simultaneously with the OE high transition or after the OE transition, output remain in a high impedance state. 13 HM674100H Series Write Cycle-5 (OE = L, WE Controlled) t WC Address t CW CS t AS WE t WZ Data Out *2 t AW t WP *1 t WR t OH t OW High Impedance t DW t DH *4 *3 Data In High Impedance Valid data High Impedance Notes: 1. A write occurs during the overlap of a low CS and a low WE (tWP). 2. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 3. Output data is the same phase of write data of this write cycle. 4. If CS is low during this period, I/O pins are in the output state. Then, the data input signals of opposite phase to the outputs must not be applied them. 14 HM674100H Series Write Cycle-6 (OE = L, CS Controlled) t WC Address t AS t CW CS t AW WE t LZ Data Out t WZ *2 t WR t WP *1 High Impedance t DW t DH Data In High Impedance Valid data Notes: 1. A write occurs during the overlap of a low CS and a low WE (tWP). 2. If CS low transition occurs after the WE low transition, output remain in a high impedance state. 15 HM674100H Series Package Dimension HM674100HJP Series (CP-32DB) Unit: mm 32 20.71 21.08 Max 17 10.16 0.13 11.18 0.13 1 3.50 0.26 1.30 Max 0.80 +0.25 -0.17 0.43 0.10 0.41 0.08 1.27 9.40 0.25 0.10 Hitachi Code JEDEC Code EIAJ Code Weight HM674100HJP -15, -20, -25 400 mil 32 pin plastic SOJ (CP-32DB) Mechanical 16 2.85 0.12 CP-32DB MO-061-AB SC-638 1.2 g 0.74 16 |
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